Cadence Announces Broad Next-Generation Memory Standard Support in Samsung Foundry’s Advanced Process Technologies


  • Cadence tapes out DDR5/4 PHY IP on Samsung 7LPP process, GDDR6 PHY
    IP on Samsung 14LPP process and HBM2 PHY IP on Samsung 10LPP process
    recharacterized to an 8LPP process
  • Cadence GDDR6 PHY IP for high-bandwidth applications achieves
    silicon success on Samsung 7LPP process
  • Cadence delivers complete, single-vendor solution for controller,
    PHY and VIP that speeds chip integration time and reduces
    interoperability risk

SAN JOSE, Calif.–(BUSINESS WIRE)–lt;a href=”” target=”_blank”gt;#EDAlt;/agt;–Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced broad
support for memory technologies across a range of Samsung Foundry’s
advanced process technologies targeting high-bandwidth applications. As
a result of the longstanding collaboration with Samsung Foundry, Cadence
has taped out DDR5/4 PHY IP on the Samsung 7nm Low Power Plus (7LPP)
process, GDDR6 PHY IP on the Samsung 14nm Low Power Plus (14LPP) process
and 2.4G High-Bandwidth Memory 2 (HBM2) PHY IP on the Samsung 10nm Low
Power Plus (10LPP) process, which has been recharacterized as the 8nm
Low Power Plus (8LPP) process. In addition, Cadence® PHY IP
for GDDR6 has achieved silicon success on the Samsung 7LPP process.
Mutual customers can begin creating designs using Samsung Foundry’s
advanced process technologies with the confidence that the Cadence DRAM
interface IP is ready for use.

For more information on the Cadence IP for GDDR6 PHY and DDR5/4, please
For more information on the Cadence IP for HBM2 PHY, visit

The Cadence IP that supports Samsung Foundry’s various advanced nodes is
intended for several emerging application areas including
high-performance computing (HPC), mobile, artificial intelligence (AI),
IoT, graphics, automated driving (AD) and adaptive driver assistance
systems (ADAS). Customers benefit from having access to a complete,
single-vendor solution for controller, PHY and Verification IP (VIP)
that speeds chip integration time and reduces interoperability risk.
Other key competitive advantages include:

  • Cadence design techniques reuse technology from Cadence’s
    silicon-proven DDR and SerDes designs, resulting in lower risk when
    implementing advanced memory technologies
  • Cadence’s low bit-error rate (BER) for GDDR6 IP reduces retries on the
    memory bus, giving applications greater bandwidth and lower maximum
  • Cadence’s design margin allows users to implement GDDR6 on PCBs using
    normal fiberglass FR4 materials, reducing the cost of GDDR6 deployment
  • Cadence’s reference design for memory interfaces allows users to
    replicate Cadence’s test chip results in their own products
  • Cadence DRAM controllers are based on the industry-leading Denali®
    DDR controller, which includes a full set of features for popular
    memory interfaces

“Cadence’s silicon success and tapeouts in Samsung Foundry’s 7LPP, 8LPP,
10LPP and 14LPP processes technologies are significant milestones in our
successful collaboration, enabling the delivery of high-performance
DDR5/4 PHY, GDDR6 PHY and HBM2 IP solutions to our mutual customers,”
said Jaehong Park, executive vice president of Design Platform
Development at Samsung Electronics. “Customers designing at advanced
nodes now have a range of Cadence’s DRAM interface IP from which to
choose, as part of the broad enablement of DRAM interfaces in Samsung
Foundry processes.”

“Samsung Electronics is a leader in state-of-the-art memory
technologies, where we have consistently been the first to enable the
most advanced memory solutions,” said Harry Yoon, vice president of
Memory Product Planning & Application Engineering at Samsung
Electronics. “In collaboration with Cadence, we will continue to expand
our premium memory lineups with high performance, high capacity and low
power consumption to support the growing demand for advanced
high-bandwidth applications, including HPC, AI and ADAS.”

“By utilizing the latest technologies from Samsung Electronics, we’re
continuing to drive advanced-node innovation as evidenced with our GDDR6
PHY IP silicon success and our latest DDR5/4 PHY, GDDR6 PHY and HBM2 IP
tapeouts,” said Amjad Qureshi, corporate vice president, R&D, Design IP
at Cadence. “Our mutual customers can access all the simulation and
emulation data required to ensure designs will work as intended, and
we’re ready to engage with customers now.”

Technology Specifications

Customers using Samsung’s advanced nodes and the Cadence IP can achieve
the following performance specifications:

  • GDDR6 technology using Cadence IP allows up to 512Gbit/sec between the
    host CPU and a single GDDR6 die
  • HBM2 technology using Cadence IP allows up to 2400Gbit/sec bandwidth
    between host CPU and a single stack of HBM2
  • DDR5 technology using Cadence IP allows up to 128Gbytes of DRAM per


Cadence PHY IP for GDDR6, DDR5/4 and HBM2, as well as memory models, are
available now for customer engagements. Design files are also ready for
select customers to begin integration work.

About Cadence

Cadence enables electronic systems and semiconductor companies to create
the innovative end products that are transforming the way people live,
work and play. Cadence’s software, hardware and semiconductor IP are
used by customers to deliver products to market faster. The company’s
System Design Enablement strategy helps customers develop differentiated
products—from chips to boards to systems—in mobile, consumer, cloud
datacenter, automotive, aerospace, IoT, industrial and other market
segments. Cadence is listed as one of Fortune Magazine’s 100 Best
Companies to Work For. Learn more at

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